1. Field of the Invention
The present invention generally relates to a system for identifying and analyzing systematic defects in integrated circuits.
2. Description of the Related Art
Systematic defects in a semiconductor process are those defects which are not a result of particles interfering with exposure or other process steps during manufacturing. Instead, systematic defects relate to layout design flaws or processing design flaws and will occur regularly at the same location within a finished product. Yield characterization engineers face a difficult task in identifying the cause of such defects. Particularly, in modern processes requiring resolution enhancement, chemo-mechanical polishing and other complex steps, the root cause often involves the interaction of a particular local pattern with the shapes in its context. The same pattern which results in a deterministic fail (or is not robust to process variations) in a particular part may not fail in other locations on the same design, or on a different design.